1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device having improved field shield isolation for electrically isolating devices formed on a common substrate.
2. Description of the Background Art
Conventionally, a method for isolating semiconductor devices has generally used an LOCOS (Local Oxidation of Silicon) process which is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 190869/1987.
FIG. 10 is a cross-sectional view showing a structure for isolation using this LOCOS process.
In FIG. 10, isolation oxide films 52a and 52b are formed at predetermined spacing so as to define an active region on a major surface of a p-type semiconductor substrate 51. n.sup.+ -type impurity regions 54a and 54b are formed at predetermined spacing in the active region. A gate electrode 55 is formed over the major surface of the semiconductor substrate 51 serving as a channel region between the impurity regions 54a and 54b through an insulating film. An interlayer insulating film 56 is formed on an entire major surface of the semiconductor substrate 51 so as to cover the gate electrode 55. An interconnection layer 57 is formed on the interlayer insulating film 56. The gate electrode 55 and the impurity regions 54a and 54b constitute a field effect transistor Tr.
Thus, the isolation oxide films 52a and 52b are formed to electrically isolate a region where this transistor is formed from another active region. However, bird's beaks 53a and 53b peculiar to the LOCOS process are formed in respective ends of the isolation oxide films. Each of the isolation oxide films extends into the active region by a length c due to the bird's beaks 53a and 53b. This brings about the narrow channel effect by which a threshold value of a field effect transistor becomes larger as the channel length thereof is decreased when isolation oxide films are formed in a channel width direction of the transistor. There are limitations of the application of the LOCOS process to fine isolation with higher integration density of the semiconductor device due to the above described length c.
FIG. 11 is a cross-sectional view showing a structure produced by field shield isolation used as isolation which can correspond to miniaturization of devices.
The structure shown in FIG. 11 is disclosed in Japanese Patent Laying Open No. 47437/1985. In FIG. 11, n.sup.+ -type impurity regions 104a and 104b are formed at predetermined spacing on a major surface of a p-type semiconductor substrate 101. A gate electrode 106 is formed over a channel region of the semiconductor substrate 101 between the impurity regions 104a and 104b through an insulating film 102. The gate electrode 106 and the impurity regions 104a and 104b constitute a field effect transistor Tr. Field shield electrodes 109a and 109b are respectively formed through the insulating film 102 in regions outside of the impurity regions 104a and 104b, i.e., above portions corresponding to the regions where the isolation oxide films are respectively formed in FIG. 10. Since the field shield electrodes 109a and 109b are respectively connected to ground power supplies 113a and 113b through variable power supplies 112a and 112b, each of the field shield electrodes 109a and 109 b is held at a negative potential. An interlayer insulating film 110 is formed over an entire surface to cover the gate electrode 106 and the field shield electrodes 109a and 109b.
Isolation between devices is achieved by holding the field shield electrodes 109a and 109b at a negative potential as described above such that the conductivity type of a region on a major surface of the semiconductor substrate 101 below the field shield electrodes is not reversed.
FIGS. 12A through 12F are cross-sectional views showing the steps of a method for manufacturing the semiconductor device shown in FIG. 11.
Referring now to FIGS. 12A to 12F, the manufacturing method therefor will be described.
An oxide film 102 and a polysilicon (polycrystalline silicon) layer 103 of a predetermined thickness are sequentially formed on a major surface of a p-type semiconductor substrate 101 as shown in FIG. 12A.
The polysilicon layer 103 and the oxide film 102 are patterned using photolithographic techniques, to form polysilicon patterns 103a, 103b and 106 at predetermined spacing. Within the prescribed spacing produced by patterning, n-type impurities are implanted into the semiconductor substrate 101 exposed by the patterning, to form n.sup.+ -type impurity regions 104a and 104b as shown in FIG. 12B.
Then, the polysilicon patterns 103a and 103b are removed by etching process using a mask of resist pattern which covers the pattern 106 (see FIG. 12C), and an oxide film 107 is formed on an entire surface of the semiconductor substrate 101 so as to cover the remaining polysilicon pattern 106 as shown in FIG. 12D.
Then, a polysilicon layer 108 is formed on an entire surface of the oxide film 107 by CVD process as shown in FIG. 12E, and the polysilicon layer 108 is patterned in a predetermined position using photolithographic techniques, to form polysilicon patterns 109a and 109b each serving as a field shield electrode as shown in FIG. 12F.
The semiconductor device having the structure shown in FIG. 11 is completed through the steps of further forming an interlayer insulating film and an interconnection layer.
Meanwhile, in the above described manufacturing method, the field shield electrodes 109a and 109b are patterned after impurity regions 104a and 104b serving as a source-drain region are formed. Therefore, high-precision mask alignment is required to form field shield electrodes. Thus, the manufacturing method is not necessarily suitable for miniaturization of devices. In addition, since the oxide films 102 and 107 under the field shield electrodes 109a and 109b are formed through two steps (FIGS. 12C and 12D), the reliability as a field effect transistor is decreased if a field shield electrode is considered as a gate electrode of a transistor for isolation.
As a partial solution to these problem, a method for manufacturing a semiconductor device in which impurity regions serving as a source-drain region are formed by self-alignment utilizing a field shield electrode as a mask is disclosed in, for example, Japanese Patent Laying-Open No. 162353/1987.
FIGS. 13A to 13G are cross-sectional views showing the steps of the manufacturing method disclosed in the above described gazette.
Referring now to FIGS. 13A to 13G, the manufacturing method will be described.
An oxide film 202 of a predetermined thickness is formed on a major surface of a p-type semiconductor substrate 201 as shown in FIG. 13A and then, a polysilicon layer 203 of a predetermined thickness is formed thereon as shown in FIG. 13B.
The polysilicon layer 203 is patterned using photolithographic techniques, to form polysilicon patterns 204a, 204b and 204c at predetermined spacing as shown in FIG. 13C.
Then, the exposed oxide film 202 is removed by an etching process using the patterns 204a, 204b and 204c as masks and then, an oxide film 205 is formed on the major surface of the semiconductor substrate 201 and an oxide film 206 is formed on upper surfaces and side surfaces of the polysilicon film patterns 204a, 204b and 204c by thermal oxidation as shown in FIG. 13D.
A polysilicon layer is formed on an entire surface of the oxide films 205 and 206 and is patterned using photolithographic techniques, so that polysilicon film patterns 207a and 207b are formed on the oxide film 205 and a polysilicon film pattern 208 is formed on the oxide film 206 as shown in FIG. 13E.
Then, n-type impurities are implanted into the major surface of the semiconductor substrate 201 through the exposed oxide film 205 and are diffused, to form impurity regions 209a, 209b, 209c and 209d as shown in FIG. 13F.
Additionally, an interlayer insulating film 210 is formed on an entire surface to cover the polysilicon film patterns 207a, 207b and 208, so that a contact hole 211 is formed such that a part of the polysilicon film pattern 204a is exposed. A metal layer is formed on the interlayer insulating film 210 including the inside of the contact hole 211 and is patterned, so that a metal interconnection 212 is formed as shown in FIG. 13G.
As described in the foregoing, in the above described method, since a field shield electrode has been already formed before impurity regions serving as a source-drain region are formed, the impurity regions are formed by self-alignment, so that high-precision mask alignment is not required. Thus, the above described method is suitable for high integration density of devices.
FIG. 14 is a cross-sectional view showing a structure around a field shield electrode in a semiconductor device in the above described manufacturing method shown in FIGS. 13A to 13G and an enlarged view of portions shown in FIG. 13G.
In FIG. 14, a polysilicon film pattern 207a serving as a gate electrode and impurity regions 209a and 209b serving as a source-drain region constitute a field effect transistor Tr.1. On the other hand, a polysilicon film pattern 207b serving as a gate electrode and impurity regions 209c and 209d serving as a source-drain region constitute a field effect transistor Tr.2. Meanwhile, the impurity region 209b in the transistor Tr.1, the impurity region 209c in the transistor Tr.2, and a polysilicon film pattern 204b serving as a field shield electrode constitute a field transistor FTr. Thus, an active region where the transistor Tr.1 is formed and an active region where the transistor Tr.2 is formed are isolated by holding the field shield electrode 204b at a predetermined potential so that the transistor FTr. always remains off. However, as shown in FIG. 14, in many cases, a conductor 208 serving as an interconnection layer is formed over the field shield electrode 204b through an insulating film 206. Therefore, there is no problem when the field shield electrode 204b is always held at a negative potential by connection to the power supply as shown in FIG. 11, while there occurs a problem when the potential thereof is electrically floating. More specifically, when the field shield electrode 204b is electrically floating, a capacitance is formed between the field shield electrode 204b and the conductor 208 by a potential applied to the conductor 208, so that the potential of the field shield electrode 204b is changed. In FIG. 14, since the field transistor FTr. is an N channel transistor, the field shield electrode 204b is raised to a predetermined potential or more. Thus, this transistor is turned on when a potential of the impurity region 209c is V.sub.D and a potential of the impurity region 209b is a ground potential. In particular, since this transistor FTr. is an overlap type transistor, the threshold value thereof is small, so that the above described problem becomes significant. More specifically, in the state shown in FIG. 13F, the oxide film 206 on the sidewalls of the field shield electrode 204b is thin because it is formed by thermal oxidation. Impurities are implanted utilizing as masks the field shield electrode 204b and the oxide film 206. Therefore, the impurity regions 209b and 209c formed by thermal diffusion of the impurities extend into a region under the field shield electrode 204b, that is, are overlapped with the field shield electrode 204b in the perpendicular direction to the major surface of the semiconductor substrate 201 (see a length a of the overlap portion). The thickness of SiO.sub.2 on polysilicon 204b formed by oxidation of polysilicon results in greater thickness than SiO.sub.2 layer 205. The thickness typically depends on impurity concentration by a layer having a few times thickness. Since the layer 205 will form the gate insulator of an FET, it must be limited in thickness, for example to approximate 200.ANG.. Therefore, the thickness of the oxide film 206 formed on opposite sides of the electrode 204b will be limited to about 1000.ANG.. This lateral distance is insufficient to prevent diffusion of implanted impurities into a region under the field shield electrode during necessary subsequent thermal annealing. Since the transistor FTr. has the same structure as that of the ordinary field effect transistor for an on-off operation, the threshold voltage thereof is small, so that the transistor FTr. is likely to be erroneously turned on. As a result, the reliability for isolation is decreased.